One of the most difficult problems in web research is security. Cryptography is the fundamental technique utilized in secure communication. One key element of cryptography is Public-Key Cryptography (PKC). In many PKCs, the Modular Exponentiation (ME) with large modulus is a crucial process. Efficient architecture design and hardware implementation of large integer Modular Exponentiation (ME) plays a vital role in computer science such as public key cryptography. Therefore, many researchers have devoted special interest to provide efficient architecture design and hardware implementation of large integer ME. This study presents and evaluates a novel architecture for the hardware implementation of ME. To achieve the maximum architectural and timing improvements, the critical path of the Left-to-Right (LtR) and Right-to-Left (RtL) ME architectures is reorganized and reordered using a modified modular multiplication. The implementation results on a Xilinx Virtex 5 FPGA demonstrate that the developed ME architectures have a better performance in comparison with other well-known ME architectures so far in the literatures.
